A Novel Vlsi Based Cryptocoding Technique Using Error Control Algorithm

This paper presents a hardware implementation for Encoder and Decoder of the cryptography technique using versatile Error Control Algorithms of Block Codes used in wireless communication networks. This work is focused on the designing of VLSI based hardware implementable and more secured alternative of existing software based symmetric cryptography techniques using DES (Data Encryption Standard) and AES (Advanced Encryption Standard Algorithm). In this design process, traditional methods of sub key generation using bit shifting along with modulo 2 addition, performance of padding and puncturing the bits of words are done so as to maintain the reliability of the design at par with conventional technique. In this design, (7,4) Block code with hamming code algorithm is considered as it has very low probability to retrieve originality without specific syndrome analysis and can be easily penetrated between any number of bits of original message as required by the Cryptography. This design is simulated and the synthesis report is generated using Verilog coding of Xilinx ISE software and the modules and results are illustrated. The report and result reveals that the proposed design will occupy very lesser number of components with reliable performance. This will lead to the small amount of power consumption and compactness in hardware implementation. Also, it is observed that the even though the used key size is small, the complexity for the intruder to retrieve the original message is greatly increased by incorporating the variety of hardware diversifying practice without sacrificing the strength of required cryptography technique. The test result shows the significance of the proposed design as the same set of message never produces the same set of cipher text. So that the computational attacks using software based iteration can not be used to track the plain text.